SinisterDeath said:
It makes sense if you understand the ps3.
In most comparison tests, the ps3 and 360 are equal.
The Cell Processor however, CAN be more powerful, like, 10x more powerful than the 360's cpu & GPU, if used CORRECTLY.
And that 'correctness' mostly has to do, with programming games, around the cell. They could have made it 'easy', so to speak, but that would make the 'total power' that the developers working on, less. Making it 'harder', will allow them to do 'more'...
Kinda think of it like this.
Its easy to carry a brick of gold up hill. But the reward is significantly greater, if you can carry several bricks of gold up hill.
Now, what Sony COULD have done, if its as 'deliberate' as the OP made it sound. They could have released 'advanced' tools for the 'advanced' games, and 'easy' tools, for the 'easy' games.
No.
GPU
"The 360 GPU is more powerful. It has more powerful fillrate, and far more pixel and vertex processing horsepower. Part of the reason is their choice of memory, and architecture of pixel and vertex procesing. I can't get into details but the same vertex shader will run much slower on the PS3 than the XBOX 360. The 360 also has a clever new way rendering high definition anti aliased back buffers. To accomplish the same effect on PS3 is prohibitively expensive. For this reason I think many games will have no choice but to run in non-HD resolutions on the PS3 version, use a lower quality anti aliasing technique, or do back buffer upscaling. The end result in all cases is going to be noticeably worse image quality."
---------------
CPU
"Theoretically, the Xenon can achieve a maximum performance of 116 gigaflops, while the Cell, in combination of the PPE and the 8 SPEs can achieve a maximum of 205 Gigaflops. But in reality, these numbers are never reached, due to inefficiencies in the architecture. But the question here is, which CPU gets closer to its maximum theoretical performance? For this, we have to identify where in the architecture potential bottlenecks can occur.
In the Xenon, each core is independent of the other, meaning what goes on in one core does not affect the other. In the Cell, the SPEs are dependent on the PPE for tasks to be issued to them. This may not be a problem normally, but if the PPE is under significant computational load, that can affect how it handles the SPEs, thus the SPEs may end up waiting for an overworked PPE to deliver them tasks. Additionally, the Cell only supports two hardware threads, raising the possibility that not enough tasks can be put on two threads to keep the SPEs busy, in some situations. The Xenon supports 6 hardware threads (2 per core), allowing to be more effective at multitasking. Thus, the cores can be kept busy more of the time.
Another issue is the element interconnect bus (EIB) on the Cell. Originally, IBM had wanted to use a crossbar to connect all the cores, but the number of transistors would have become prohibitively high. So to save die space, IBM went with a ring bus-type interconnect. This has lower bandwidth and higher latency than a crossbar, which can induce delays within the CPU, especially during periods of peak data transfer. The cores on the Xenon communicate over a crossbar and through the shared L2 cache, much like how cores communicate on Intel's Core 2 Duo architecture.
The SPEs in the Cell are also limited in what types of instructions they can execute. For any instruction that cant be handled by the SPEs, they must be handled by the PPE. This limits the Cell's capability in some instances. It also puts more load on the PPE and again can overload the PPE, leaving the SPEs waiting for tasks to be issued. The Xenon has 3 cores that can handle any type of task given to them. While not as powerful as the Cell, it is more flexible.
Yet another issue brought up is the Cell's on die memory controller. It has been claimed that this gives it an advantage over the Xenon, as had been said about AMD's CPUs compared to Intel's. However, with the advent of the Core 2 Duo, the memory controller claims were debunked, the location of it has a negligible impact on performance, whether on die or not. It should be noted that the Cell uses a serial bus to connect to the memory. The XDR RAM used is designed by Rambus and is based on RDRAM. For anyone who remembers RDRAM, it had more bandwidth than the parallel DDR modules used at the time, but the latency was very high. So high in fact that it negated any speed advantage it had over DDR, and was eventually phased out. While XDR is improved, it still has higher latencies than the GDDR3 memory used on the 360.
Also, it should be brought up that you don't have all 8 SPEs in the Cell available for gaming. One is disabled for yield improvement, one is reserved exclusively for the operating system, even if not being used. Another can be taken by the operating system if needed. This only leaves 5 SPEs available to the game at any given time. It should also be noted that the SPEs lack branch prediction. One of the claims made is that the Cell is far better for AI and physics. While this is true for physics calculations, AI code is extremely branch intensive and is filled with conditional statements. Thus, the Cell's performance suffers when it comes to AI, as only the PPE features branch prediction. The Xenon is better suited for AI in this case, as all three of its cores include branch prediction.
Despite its shortcomings, the Cell is still an incredibly powerful processor. However, the Xenon is not too far behind. And the fact that the R500 features a programmable tessalator may even negate any speed advantage that the Cell has - when it comes to gaming anyways."
/thread.